RISC-V /Debug /Exception Trigger (64-bit etrigger)

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Interpret as Exception Trigger (64-bit etrigger)

63 6059 5655 5251 4847 4443 4039 3635 3231 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (breakpoint)action0 (u)u0 (s)s0 (m)m0 (vu)vu 0 (vs)vs 0 (hit)hit 0 (dmode)dmode 0type

action=breakpoint

Description

This register provides access to the trigger selected by {csr-tselect}. The reset values listed here apply to every underlying trigger.

This register is accessible as {csr-tdata1} when {tdata1-type} is 5.

This trigger may fire on up to XLEN of the Exception Codes defined in mcause (described in the Privileged Spec, with Interrupt=0). Those causes are configured by writing the corresponding bit in {csr-tdata2}. (E.g. to trap on an illegal instruction, the debugger sets bit 2 in {csr-tdata2}.)

đź“Ś NOTE

If XLEN is 32, then it is not possible to set a trigger on Exception Codes higher than 31. A future version of the RISC-V Privileged Spec will likely define Exception Codes 32 through 47.

Hardware may support only a subset of exceptions. A debugger must read back {csr-tdata2} after writing it to confirm the requested functionality is actually supported.

When the trigger matches, it fires after the trap occurs, just before the first instruction of the trap handler is executed. If {etrigger-action}=0, the standard CSRs are updated for taking the breakpoint trap, and zero is written to the relevant tval CSR. If the breakpoint trap does not go to a higher privilege mode, this will lose CSR information for the original trap. See nativetrigger for more information about this case.

If {csr-textra32} or {csr-textra64} are implemented for this trigger, it only matches when the conditions set there are satisfied.

Fields

action

The action to take when the trigger fires. The values are explained in tab:action.

0 (breakpoint):

1 (debug mode):

2 (trace on):

3 (trace off):

4 (trace notify):

8 (external0):

9 (external1):

u

When set, enable this trigger for exceptions that are taken from U mode. This bit is hard-wired to 0 if the hart does not support U-mode.

s

When set, enable this trigger for exceptions that are taken from S/HS mode. This bit is hard-wired to 0 if the hart does not support S-mode.

m

When set, enable this trigger for exceptions that are taken from M mode.

vu

When set, enable this trigger for exceptions that are taken from VU mode. This bit is hard-wired to 0 if the hart does not support virtualization mode.

vs

When set, enable this trigger for exceptions that are taken from VS mode. This bit is hard-wired to 0 if the hart does not support virtualization mode.

hit

If this bit is implemented, the hardware sets it when this trigger matches. The trigger’s user can set or clear it at any time. It is used to determine which trigger(s) matched. If the bit is not implemented, it is always 0 and writing it has no effect.

dmode
type

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